1. Field of the Invention
The present invention relates to fault analysis of a semiconductor integrated circuit device and, more particularly, to a method of detecting and locating a fault portion in a CMOS logic integrated circuit where a power supply current (to be referred to as IDDQ hereinafter) flowing in an inoperative state exhibits an abnormal value.
2. Related Background Art
As a fault portion detection method of detecting a fault with an abnormal IDDQ in a CMOS logic circuit, the emission analysis method using an emission microscope (EMS) is used.
In this method, the operation pattern of a CMOS logic circuit is input by an LSI tester or the like, and an operation pattern in which the IDDQ exhibits an abnormal value is detected. The abnormal IDDQ pattern is input, and in this state, light emission according to the abnormal current is observed by EMS.
The light emitting portion observed by EMS is etched up to a predetermined layer, and the physical abnormality is observed with an optical microscope or electron microscope, as needed.
In addition, the internal wiring of the CMOS logic circuit is irradiated with an electron beam or brought into direct contact with a metal needle, and the operation waveform of the internal wiring is observed. A simulation is done on the basis of the design data of the CMOS logic circuit to locate the fault portion.
In the fault portion locating method using EMS, recombination light emission in the semiconductor element section is detected. When the fault mode is a low-resistance short-circuiting between metal film wirings or an open fault, light emission by EMS occurs not at the physically abnormal portion (short-circuiting between circuit wirings or open) but at the semiconductor element section connected to the abnormal portion. The element that emits light by EMS is one of signals representing a physical abnormality, though it does not always coincide with the actual fault. For this reason, an erroneous portion may be analyzed by subsequent physical analysis.
In addition, since the method using simulation always requires design information of the corresponding integrated circuit, the method can be implemented only on the maker side (designer side) of the integrated circuit.
It is an object of the present invention to locate a physical abnormality portion of a low-resistance short-circuiting between signal wirings or open fault in a CMOS logic circuit without using design information.
In the present invention, first, the operation test pattern of a semiconductor integrated circuit device such as a CMOS logic circuit is input by, e.g., an LSI tester, and an abnormal IDDQ pattern in all operation test patterns is detected. Changes in abnormal IDDQ in all operation test patterns can be classified into several modes. Taking this fact into consideration, the abnormal IDDQ change modes in all operation test patterns are defined.
Next, the defined abnormal IDDQ change modes are made to correspond to supposed physical abnormalities in advance to prepare a first information table. A change in abnormal IDDQ of an actual abnormality is compared with data in this table to firstly narrow the range of locating the physical abnormality.
A light emitting element by EMS in each abnormal IDDQ pattern is detected. A change of the light emitting element is made to correspond to a model of physical abnormality in advance to prepare a second information table. The EMS analysis result of an actual abnormality is compared with data in this table to secondly narrow the range of locating the physical abnormality. With this analysis method, the physically abnormal portion can be accurately detected and located by combining these narrowing results.